PURPOSE: To always supply optimum current to a bit line and to expand operational margin by providing a constant current circuit in using a dummy cell of the same circuit as a memory cell in the sense amplifier circuit block of a static RAM.
CONSTITUTION: The dummy cells MC1, MC2 of the same circuit as the memory cell is used as a reference current circuit to represent the read status of the memory cell. Since the collectors of the switching transistors Q116, Q122 of the cells MC1, MC2 are open, an inbalance occurs in the internal status of the cells MC1, MC2, accordingly switching transistors Q115, Q121 inevitably turn on. Consequently, the reference current circuit receives a current double that a memory cell can receive from an output terminal Ref, and supplies this current to a bit line via a current mirror circuit. Therefore, without saturating the switch transistor of a memory cell, the operational condition of a bit line can always be satisfied, hence the operational margin can be expanded.
| JPS63138592 | READING/WRITING CONTROL CIRCUIT |
| JP2569986 | SEMICONDUCTOR MEMORY DEVICE |
| JPS58220292 | SEMICONDUCTOR MEMORY |
HAYASHI MAKOTO
WATABE TOMOYUKI
FURUHATA MAKOTO
HITACHI VLSI ENG
| JPS5956290A | 1984-03-31 | |||
| JPS58159294A | 1983-09-21 | |||
| JPS5694577A | 1981-07-31 |