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Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS63127539
Kind Code:
A
Abstract:

PURPOSE: To prevent the crack of a passivation film and the slip of a wiring by making the section of a passivation film which covers the topmost layer wiring on a semiconductor substrate have a slower angle than 90 degrees against the surface of the semiconductor substrate at the side of the wiring.

CONSTITUTION: The section of an electrically insulating film which covers the topmost layer of wiring layers is made to have nearly a linear shape of smaller angle than 90 degrees against the surface of a semiconductor substrate at the side of the wiring layers. That is, after an interlayer insulating film 4 is provided, the second layer wiring 5 connected to the first layer wiring 3 via a through hole is formed and a passivation film 6 is coated on the semiconductor substrate 1 which includes the second layer wiring 5 to approx. 5000 by bias sputtering. By this method, the section which is the step difference before coating and especially, to which the greatest stress is applied at the side of the second layer wiring 5 can be made an angle of approx. 45 degrees against the surface of the semiconductor substrate 1. This can give great strength against the stress due to the difference of thermal expansions between a mold resin, the semiconductor substrate 1 and the passivation film 6.


Inventors:
YORIKANE MASAHARU
Application Number:
JP27469186A
Publication Date:
May 31, 1988
Filing Date:
November 17, 1986
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L21/31; (IPC1-7): H01L21/31; H01L21/95
Domestic Patent References:
JPS5441673A1979-04-03
JPS58166929A1983-10-03
JPS60202942A1985-10-14
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
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