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Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS63164473
Kind Code:
A
Abstract:

PURPOSE: To prevent a latchup in a vertical bipolar MOSFET by forming the same conductivity type diffused layer as that of a channel diffused layer at the periphery of a channel diffused layer, and connecting it to a source electrode.

CONSTITUTION: The same conductivity type p-type diffused layer 11 as a p-type diffused layer (channel diffused layer, base) 5 is formed around the layer 5, and electrically connected to an emitter electrode 1. When thus constructed, when a positive gate voltage is applied to a gate electrode 3, the surface of the layer 5 is first inverted to n-type, and an electron current (d) flows from a source (emitter) side to a drain side. Thus, diffused holes from a p-type layer 9 branched to a, c, e, f. In this manner, a hole current to be implanted to the layer 5 which cause a latchup can be largely reduced.


Inventors:
MIHARA TAKAYUKI
YAMANAKA KAZUO
SUEYOSHI SATOSHI
Application Number:
JP31497586A
Publication Date:
July 07, 1988
Filing Date:
December 26, 1986
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H01L29/68; H01L29/10; H01L29/739; H01L29/78; H01L29/06; (IPC1-7): H01L29/68; H01L29/78
Attorney, Agent or Firm:
Sadaichi Igita



 
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