Title:
半導体装置、電子部品、および電子機器
Document Type and Number:
Japanese Patent JP6866232
Kind Code:
B2
Abstract:
A semiconductor device including a memory which can perform a pipeline operation is provided. The semiconductor device includes a processor core, a bus, and a memory section. The memory section includes a first memory. The first memory includes a plurality of local arrays. The local array includes a sense amplifier array and a local cell array stacked thereover. The local cell array is provided a memory cell including one transistor and one capacitor. The transistor is preferably an oxide semiconductor transistor. The first memory is configured to generate a wait signal. The wait signal is generated when a request for writing data to the same local array is received over two successive clock cycles from the processor core. The wait signal is sent to the processor core via the bus. The processor core stands by for a request for the memory section on the basis of the wait signal.
Inventors:
Tatsuya Onuki
Uesugi Wataru
Uesugi Wataru
Application Number:
JP2017099875A
Publication Date:
April 28, 2021
Filing Date:
May 19, 2017
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
G11C11/4096; H01L21/8242; H01L27/10; H01L27/108; H01L29/786
Domestic Patent References:
| JP2000057761A | ||||
| JP2013065638A | ||||
| JP2017028237A | ||||
| JP2000090664A | ||||
| JP11317072A | ||||
| JP4082735U | ||||
| JP2012256821A | ||||
| JP2007250121A |
Foreign References:
| US20160104521 |