Title:
半導体装置及び半導体回路
Document Type and Number:
Japanese Patent JP7297709
Kind Code:
B2
Abstract:
A semiconductor device according to an embodiment including: a semiconductor layer having a first plane and a second plane, the semiconductor layer including: a first trench on the first plane; a second trench on the second plane; a first conductivity first semiconductor region; a second conductivity type second semiconductor region between the first semiconductor region and the first plane; a first conductivity type third semiconductor region between the second semiconductor region and the first plane; a second conductivity type fourth semiconductor region between the third semiconductor region and the first plane; and a first conductivity type fifth semiconductor region provided between the second trench and the third semiconductor region in contact with the second trench; a first gate electrode in the first trench; a second gate electrode in the second trench; a first electrode on the first plane; and a second electrode on the second plane.
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Inventors:
Tomoko Sueshiro
Yoko Iwao
Yoko Iwao
Application Number:
JP2020050275A
Publication Date:
June 26, 2023
Filing Date:
March 19, 2020
Export Citation:
Assignee:
Toshiba Corporation
Toshiba Electronic Devices & Storage Corporation
Toshiba Electronic Devices & Storage Corporation
International Classes:
H01L29/78; H01L29/739
Domestic Patent References:
JP2017054968A | ||||
JP2001320049A | ||||
JP2018082058A | ||||
JP2017174961A | ||||
JP2005340626A | ||||
JP2019186318A | ||||
JP2013251296A | ||||
JP2010123667A | ||||
JP2012084722A | ||||
JP2004103980A |
Attorney, Agent or Firm:
Tetsuma Ikegami
Akira Sudo
Masahiro Koshita
Akira Sudo
Masahiro Koshita