Title:
半導体装置、固体撮像素子、並びに電子機器
Document Type and Number:
Japanese Patent JP7123813
Kind Code:
B2
Abstract:
The present technology relates to a semiconductor device and a manufacturing method therefor, a solid-state imaging element and electronic equipment suitable that make it possible to suppress breakdown of a side wall insulating film by charge damage to suppress short-circuiting that could have occurred between a semiconductor substrate and a through electrode.The semiconductor device according to an aspect of the present technology includes a first semiconductor substrate on which a given circuit is formed, a second semiconductor substrate pasted to the first semiconductor substrate, and through electrodes that electrically connect the first semiconductor substrate and the second semiconductor substrate to each other. The through electrode is formed such that a through-hole is opened through a protection diode structure formed in the first semiconductor substrate, an insulating film is deposited on a side wall of the through-hole, and an electrode material is then filled inside the through-hole in which the insulating film is deposited. The present technology can be applied, for example, to a CMOS image sensor.
Inventors:
Hiroshi Takahashi
Application Number:
JP2018564457A
Publication Date:
August 23, 2022
Filing Date:
January 10, 2018
Export Citation:
Assignee:
Sony Semiconductor Solutions Corporation
International Classes:
H01L27/146; H01L21/3205; H01L21/768; H01L21/822; H01L23/522; H01L25/065; H01L25/07; H01L25/18; H01L27/04; H04N5/369
Domestic Patent References:
| JP2011204915A | ||||
| JP2013251391A |
Foreign References:
| WO2015068588A1 | ||||
| WO2016009943A1 | ||||
| US20130119502 | ||||
| WO2005101475A1 | ||||
| US20140061874 | ||||
| US20100079638 |
Attorney, Agent or Firm:
Takashi Nishikawa
Yoshio Inamoto
Yusuke Miura
Yoshio Inamoto
Yusuke Miura