To provide a method for manufacturing a semiconductor element, capable of using an optimum manufacturing technique to provide the element reduced in size of an overall semiconductor element, to form a memory cell and to form a logic circuit.

The semiconductor element comprises a first semiconductor substrate having a memory cell area formed thereon, and a second semiconductor substrate having a logic circuit area formed thereon. The second substrate is laminated on the first substrate to operate the memory cell area by the logic circuit area. The method for manufacturing the semiconductor element comprises a step of forming the memory cell on the first substrate, a step of forming the logic circuit on the second substrate, and a step of laminating the first substrate and the second substrate and electrically connecting both the first and second substrates to operate the cell by the logic circuit.