SEMICONDUCTOR ELEMENT WITH BUMP, ITS FABRICATION PROCESS, MODULE EMPLOYING THE SEMICONDUCTOR ELEMENT WITH BUMP

Title:

SEMICONDUCTOR ELEMENT WITH BUMP, ITS FABRICATION PROCESS, MODULE EMPLOYING THE SEMICONDUCTOR ELEMENT WITH BUMP

Document Type and Number:

Japanese Patent JP2007305723

Kind Code:

A

Abstract:

To provide a semiconductor element with bump in which good connection reliability is achieved between the semiconductor element with bump and a circuit board.

The semiconductor element with bumps comprises a substrate 3, a semiconductor circuit provided on the substrate 3, an insulating film formed on the semiconductor circuit, a portion on the insulating film where the insulating film is not formed, and a conductor pad 6a formed in the portion where the insulating film is not formed and connected with the semiconductor circuit wherein the conductor pad 6a is connected with a transfer bump 8 formed by intaglio transcription. Since the clearance 25 can be enlarged between a circuit board 7 and a semiconductor element, thermal stress generated due to difference of linear expansion coefficient can be relaxed between the semiconductor element 1 with bump and the circuit board 7.

Inventors:

KIMURA JUNICHI
HARADA SHINJI
UENISHI KENJI

Application Number:

JP2006131341A

Publication Date:

November 22, 2007

Filing Date:

May 10, 2006

Export Citation:

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Assignee:

MATSUSHITA ELECTRIC IND CO LTD

International Classes:

H01L21/60

Attorney, Agent or Firm:

Fumio Iwahashi
Hiroki Naito
Daisuke Nagano

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