Title:
SEMICONDUCTOR IC DEVICE
Document Type and Number:
Japanese Patent JPS6074647
Kind Code:
A
Abstract:
PURPOSE:To contrive to improve the strength against the phenomenon of latch- up and the integration degree by a method wherein a contact diffused region of one conductivity type to a semiconductor substrate and a contact diffused region of reverse conductivity type to a well are connected to different power source wirings. CONSTITUTION:The contact diffused regions to the semiconductor substrate and the well are formed e.g. by three-division in the P type well 9 interposed between P-channel type transistors TR1, TR2 and N-channel type transistors TR3, TR4 and in the region of the surface of the N type Si semiconductor substrate 10 where gate electrode wiring layers 1 and 2 are not mounted. Contact diffused regions 17a-17c and 18a-18c formed by alignment with isolation oxide films 16, and the regions 17a-17c to the substrate are formed at the same time with the source and drain regions 3-5 of the N-channel transistor. The regions 18a-18c to the P type well are formed at the same time with the source and drain regions 6-8 of the P-channel transistor.
Inventors:
TAKAYAMA YOSHIHISA
TANABE TOMOAKI
FUJII SHIGERU
TANABE TOMOAKI
FUJII SHIGERU
Application Number:
JP18203683A
Publication Date:
April 26, 1985
Filing Date:
September 30, 1983
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H01L27/08; H01L21/82; H01L27/118; H01L29/78; (IPC1-7): H01L27/08; H01L29/78
Attorney, Agent or Firm:
Sadaichi Igita