Title:
SEMICONDUCTOR IC
Document Type and Number:
Japanese Patent JPS6156432
Kind Code:
A
Abstract:
PURPOSE:To enable the generation of the withstand voltage intrinsic to the junction without adverse effects on element characteristics by a method wherein a conductor layer of fixed potential is formed on an isolation region, and the fixed potential is set at a potential whereby a depletion layer generating out of the junction of the isolation region spreads to the semiconductor layer side. CONSTITUTION:An N-type epitaxial layer 3 is formed on a P type substrate 1, and an N-P-N transistor formed in the region isolated by P type layers 2 and 2' is assumed to be turned off by the base 4 potential on condition that its collector 5 is wired to VCC (maximum potential) and its emitter 6 to the GND potential (minimum potential). The conductor layer 13 of aluminum or poly Si is provided via insulation film 7 under a wiring 8 on the VCC side which blocks the spreading of depletion layers 11 and 11'. If the overhang of the conductor layer 13, extending outside the isolation region 2, which fixes the potential of this layer 13 at GND is suitably set, then the depletion layers 11 and 11' spread over a surface of normal spreading or over a larger surface, causing no decrease in withstand voltage.
Inventors:
YOSHIDA HIROSHI
Application Number:
JP17871584A
Publication Date:
March 22, 1986
Filing Date:
August 28, 1984
Export Citation:
Assignee:
NEC CORP
International Classes:
H01L21/8222; H01L21/331; H01L21/761; H01L23/50; H01L27/06; H01L29/73; H01L29/732; (IPC1-7): H01L21/76; H01L27/08; H01L29/72
Domestic Patent References:
| JP58124953B |
Attorney, Agent or Firm:
Uchihara Shin