Title:
SEMICONDUCTOR INPUT CIRCUIT
Document Type and Number:
Japanese Patent JP3231925
Kind Code:
B2
Abstract:
PURPOSE: To provide a semiconductor input circuit which supplies appropriate threshold potential to an input signal of TTL level and with short delay time of an output signal.
CONSTITUTION: When the input signal is set in an 'H' level that is the TTL level, both a PMOS 11 and a NMOS 12 are set in an energized state. In such an energized state, the level of an output signal is decided by a resistance ratio when the PMOS 11 and NMOS 12 are energized, and the threshold potential of the input circuit is also decided by the resistance ratio when the PMOS 11 and NMOS 12 are energizeed. When the input signal changes from 'H' to 'L', PMOSs 21, 22 are set in the energized state until the potential of an output terminal Out2 exceeds the threshold potential of an inverter 23, and a resistance value between power supply potential Vd and the output terminal Out2 is decreased. Therefore, the rise delay time of the output signal can be shortened.
Inventors:
Tsunaaki Yottei
Application Number:
JP31769193A
Publication Date:
November 26, 2001
Filing Date:
December 17, 1993
Export Citation:
Assignee:
Oki Electric Industry Co., Ltd.
International Classes:
H03K19/0185; (IPC1-7): H03K19/0185
Attorney, Agent or Firm:
Yasunari Kakimoto