Title:
SEMICONDUCTOR INTEGRATED CIRCUIT AND BUS CONTROL METHOD
Document Type and Number:
Japanese Patent JP2000259558
Kind Code:
A
Abstract:
To provide high-speed information transmission and information throughput.
This circuit 100 is provided with a bus control means 114 for controlling the operation of an internal bus 113 inside the circuit 100 and an external bus 160 for connecting this circuit 100 and an external device and a storage means 111 for storing data. Furthermore, the bus control means 114 has a first release means 115 for releasing the internal bus 113 and the external bus 160 and a second release means 116 for releasing the external bus 160.
Inventors:
KANZAKI TAKESHI
Application Number:
JP6750699A
Publication Date:
September 22, 2000
Filing Date:
March 12, 1999
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
G06F13/362; G06F15/78; (IPC1-7): G06F13/362; G06F15/78
Attorney, Agent or Firm:
Hidekazu Miyoshi (7 outside)