To provide a semiconductor integrated circuit designing device and method which suppresses film thickness fluctuations in metal wiring of a signal having a strict timing margin.

In the semiconductor integrated circuit designing device 1, a designated signal metal pattern extracting part 11 extracts a metal pattern of a designated signal name from layout data stored in a memory device 1000, a metal pattern surrounding area setting part 12 sets a predetermined area surrounding the metal pattern extracted by the designated signal metal pattern extracting part 11, a metal coverage factor evaluating part 13 computes a metal coverage factor of the surrounding area set by the metal pattern surrounding area setting part 12, and determines whether the metal coverage factor is equal to or more than a given value, and when it is determined that the metal coverage factor is less than the given value, a dummy metal inserting part 14 inserts a dummy metal into the surrounding area.