SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND FABRICATION METHOD THEREOF

Title:

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND FABRICATION METHOD THEREOF

Document Type and Number:

Japanese Patent JP2001085625

Kind Code:

A

Abstract:

To reduce leakage current of a capacitive element comprising an MISFET(metal insulator semiconductor field effect transistor).

A capacitive element C1 is formed utilizing the storage area of a p-channel MISFET having a gate oxide film 9B thicker than an MISFET at a logic section. A polysilicon film constituting a part of a gate electrode 10E is doped with n-type impurities so that the capacitive element C1 can operate stably even with a low power supply voltage.

Inventors:

SUZUKI KAZUHISA
TAKAHASHI TOSHIRO
YANAGISAWA YASUNOBU
NONAKA YUSUKE

Application Number:

JP25946099A

Publication Date:

March 30, 2001

Filing Date:

September 13, 1999

Export Citation:

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Assignee:

HITACHI LTD

International Classes:

H01L27/04; H01L21/822; H01L21/8234; H01L21/8238; H01L21/8242; H01L21/8244; H01L27/06; H01L27/092; H01L27/108; H01L27/11; (IPC1-7): H01L27/04; H01L21/822; H01L27/06; H01L21/8238; H01L27/092; H01L21/8244; H01L27/11; H01L21/8242

Attorney, Agent or Firm:

Yamato Tsutsui

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