SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF

Title:

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF

Document Type and Number:

Japanese Patent JPH06151736

Kind Code:

A

Abstract:

PURPOSE: To provide a gate electrode stable in characteristics and to form a self-aligned contact(SAC) without overetching an insulating film which covers the gate electrode when the contact is bored.

CONSTITUTION: A polysilicon wiring 10 is formed on a semiconductor substrate 1, wherein a polysilicon film 5 is formed on a part of the polysilicon wiring 10 located on a gate electrode 3 to make the wiring 10 thick. Therefore, the gate electrode 3 is prevented from being doped with impurities injected into the wiring 10. When a gate SAC is formed on the semiconductor substrate 1 provided with a polysilicon gate, the polysilicon film 5 is formed on the insulating film 4 provided onto the gate electrode 3, whereby the insulating film 4 is prevented from being overetched.

Inventors:

ISHIMARU KAZUNARI

Application Number:

JP32230592A

Publication Date:

May 31, 1994

Filing Date:

November 09, 1992

Export Citation:

Click for automatic bibliography generation Help

Assignee:

TOSHIBA CORP

International Classes:

H01L21/28; H01L21/8234; H01L21/768; H01L23/485; H01L23/532; H01L27/088; (IPC1-7): H01L27/088

Attorney, Agent or Firm:

Toshi Takemura

Previous Patent: Agitating equipment and a train of gears

Next Patent: ELECTRONIC LENS