Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND METHOD FOR PREVENTING MALFUNCTION OF READING OF DIGITAL SIGNAL
Document Type and Number:
Japanese Patent JP2002135236
Kind Code:
A
Abstract:
To eliminate influence due to variations in the amount of delay in each signal, and to prevent malfunctions, when reading the signal in a high-speed LSI which needs to read a plurality of signals in synchronism.
The signal is inputted via flip-flops(FF) 5 to 7. Voltage controlled oscillators(VCO) 3b to Se are arranged around a DSP 4, each VCO is incorporated into PLLs (8, 9, 10, etc.), and the oscillation frequency and phase of each VCO are arranged. The oscillation clock of each VCO is set to the sampling clock of each of FFs 5 to 7 and the DSP 4. The layout arrangement of each VCO is determined, so that wiring delay becomes uniform.
Inventors:
AMAN NORIHISA
Application Number:
JP2000322606A
Publication Date:
May 10, 2002
Filing Date:
October 23, 2000
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G06F1/10; G06F1/12; H03L7/099; H04L7/033; (IPC1-7): H04L7/033; G06F1/10; G06F1/12; H03L7/099
Attorney, Agent or Firm:
Koichi Washida
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