SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD THEREFOR

Title:

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD THEREFOR

Document Type and Number:

Japanese Patent JP2005310852

Kind Code:

A

Abstract:

To inhibit increase of the contact resistance at an interface between a metal layer and a silicon plug in a wiring structure, in which the silicon plug is formed on the top of the metal layer and connected to the metal layer.

The lower conductive layer (drain) 57 of a vertical MISFET (SV1) is connected to an intermediate metal layer 42 via a plug 55 which is formed below the lower conductive layer, and comprises a polycrystalline silicon film. A trap layer 48, comprising a titanium nitride (TiN) film, is formed on part of the surface of the intermediate metal layer 42 to encircle the plug 55. The top layer 48 is formed, in order to prevent an undesired high-resistance oxide layer from being formed on the interface between the plug 55 and the intermediate metal layer 42.

Inventors:

MORIYA SATOSHI
KIKUCHI TOSHIYUKI
KONNO AKIHIKO
SATO HIDENORI
YAMAMOTO NAOKI
MATSUOKA MASAMICHI
CHAGIHARA HIROSHI
NISHIDA AKIO

Application Number:

JP2004122428A

Publication Date:

November 04, 2005

Filing Date:

April 19, 2004

Export Citation:

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Assignee:

RENESAS TECH CORP

International Classes:

H01L23/522; H01L21/768; H01L21/8244; H01L27/088; H01L27/092; H01L27/11; H01L29/76; H01L21/336; H01L21/8234; (IPC1-7): H01L21/768; H01L21/8244; H01L27/11

Attorney, Agent or Firm:

Yamato Tsutsui

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