Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
Document Type and Number:
Japanese Patent JP2010147267
Kind Code:
A
Abstract:
To provide a semiconductor integrated circuit device that suppresses the increase of defect modes due to variance in inter-pad-rewiring resistance even when an operation speed becomes fast, and to provide a method of manufacturing the same.
A barrier-metal layer including a lower-layer titanium layer, an intermediate titanium nitride layer, and an upper-layer titanium layer is interposed between an aluminum-based pad 2p and rewiring 16 of a wafer-level-package type semiconductor integrated circuit device (LSI) and the thickness of the lower-layer titanium layer is made ≥5 to ≤60 nm so as to stabilize resistance between the aluminum-based pad 2p and rewiring 16.
COPYRIGHT: (C)2010,JPO&INPIT
Inventors:
TAKAHASHI SHINO
Application Number:
JP2008323343A
Publication Date:
July 01, 2010
Filing Date:
December 19, 2008
Export Citation:
Assignee:
RENESAS TECH CORP
International Classes:
H01L23/12
Attorney, Agent or Firm:
Shizuyo Tamamura
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