Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, NON-VOLTATILE SEMICONDUCTOR STORING DEVICE AND THEIR MANUFACTURE
Document Type and Number:
Japanese Patent JP3453001
Kind Code:
B2
Abstract:
PURPOSE: To provide a non-volatile semiconductor storing device provided with improved latch up resistance, punch through breakdown strength and breakdown strength at the junction of the well area with the semiconductor substrate.
CONSTITUTION: A lightly doped P-type epitaxial layer is formed on the surface of a first semiconductor layer 101 composed of a heavily doped P-type silicon substrate. Boron (B) is implanted on the surface of the epitaxial layer heat treatment is performed and a lightly doped P-type second semiconductor layer 102 is formed. Phosphorous is implanted by masking the areas other than the desired area, heat treatment is performed and an N-type first well area 103 is formed. Boron (B) is implanted by masking the area other than the desired area phosphorous is implanted by masking the boron implanted layer, heat treatment is performed, and P-type second well areas 104a and 104b, P-type third well areas 105a-105c and N-type well areas 106a-106c are formed.
Inventors:
Hiroshi Onoda
Application Number:
JP8272195A
Publication Date:
October 06, 2003
Filing Date:
April 07, 1995
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
H01L21/8247; G11C16/02; G11C16/04; H01L27/10; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L27/10; H01L21/8247; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP277153A | ||||
| JP6285460A | ||||
| JP3105971A | ||||
| JP3290960A | ||||
| JP5326858A | ||||
| JP6216380A | ||||
| JP555530A |
Attorney, Agent or Firm:
Mamoru Takada (2 outside)
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