To lighten the load on a signal wiring in a chip without using a complicated control circuit.

Shift registers 110 and data registers 120 are divided into two blocks on a front-stage side and a rear-stage side, and paths of clock lines CL to the shift registers 110 and data lines DL to the data registers 120 are branched into two paths from the centers of the two blocks to the front-stage side and rear-stage side to be separated through gate circuits 170a and 170b, and 180a and 180b. Then the respective gate circuits are inhibited from outputting with inversion signals /SP3 to /SP5 of shift pulses SP2 to SP4 and shift pulses SP3 to SP5.

COPYRIGHT: (C)2008,JPO&INPIT