To provide a semiconductor integrated circuit device and a test method therefor in which a high speed operation test can be performed with a simple constitution and high reliability, and a manufacturing method for the semiconductor integrated circuit device in which an improved selection yield is realized with a simple constitution.
The input of a control circuit is coupled to a terminal to which an external operation control signal is supplied and a terminal to which a timing signal for test only, the internal operation control signal is changed from a first control state to a second control state responding to change from a first state to a second state of the external operation control signal at the time of a test mode, also the internal operation control signal is changed to the first control state responding to the timing for test only, the internal operation control signal is changed from a first control state to a second control state responding to change from a first state to a second state of the external operation control signal at the time of a normal operation mode, also, the internal operation control signal is changed to the first control state responding to change to the first state of the external operation control signal.
| JPH11500741 | backbone -- cyclization -- the library of a peptide analog |
| JP2008185362 | OPERATION MODE GENERATION CIRCUIT |
| JP2934149 | PROGRAMMABLE INTEGRATED LOGIC DEVICE |
MIYAOKA SHUICHI
AKASAKI HIROSHI
KATAYAMA MASAHIRO
HITACHI ULSI SYS CO LTD
Next Patent: LIGHTING MECHANISM FOR VISUAL FIELD LIGHTING DEVICE