To provide a semiconductor integrated circuit device capable of easily performing a pseudo tuning.

A power source tuning circuit is provided with plural power source circuits. Each of the power source circuits is provided with latch circuits 103 and 104. The respective latch circuits 103 and 104 record tuning signals P1 and P2. Correspondent transistors 26 and 27 are turned on/off by the recorded tuning signals. Thus, pseudo tuning is performed. After the tuning signals P1 and P2 are supplied to the latch circuits, the tuning signals P1 and P2 are supplied to the other power source circuit. Thus, a pseudo tuning can be simultaneously performed to the plural power source circuits.