SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Title:

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Document Type and Number:

Japanese Patent JP2000173297

Kind Code:

A

Abstract:

To perform efficiently a screening test in a short time by shortening an applying time of stress voltage by varying arbitrarily various internal generation power source voltage.

When a vender test mode in which voltage acceleration test is performed is selected, a level control signal is outputted from a control circuit 10, an internal power source circuit 13 varies a level of internal voltage based on this level control signal, and burn-in test is performed in an outputted state. In array stress mode, power source voltage VCC and substrate voltage VBB are the same voltage as that in a normal mode, boosting voltage VPP, dropping voltage VDL, plate voltage VPLT are leveled up respectively. After that, in a boosting voltage VPP down mode, boosting voltage VPP is dropped to nearly 4.4 V from nearly 5.4 V.

Inventors:

ITO YUTAKA

Application Number:

JP34705898A

Publication Date:

June 23, 2000

Filing Date:

December 07, 1998

Export Citation:

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Assignee:

HITACHI LTD

International Classes:

G11C11/407; G01R31/28; G11C11/401; G11C29/00; G11C29/06; H01L21/822; H01L21/8242; H01L27/04; H01L27/108; (IPC1-7): G11C29/00; G01R31/28; G11C11/407; G11C11/401; H01L27/04; H01L21/822; H01L27/108; H01L21/8242

Attorney, Agent or Firm:

Yamato Tsutsui

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