To provide constitution of a semiconductor integrated circuit device which can perform efficient detection of a fault by arbitrarily adjusting internal power source voltage in accordance with a purpose of an operation test.

In an internal voltage generating circuit 100, internal voltage VIN is set in accordance with a ratio of a resistance value Ru between a power source node 101 and an internal node N1 and a resistance value Rd between a ground node 102 and an internal node N2. An internal voltage switching control circuit 110 generates control signals VUP and VWD in accordance with test mode signals /TACU, /TACD and /TSBU, and /TSBD set independently in an active state and a standby state respectively at the time of an operation test. The internal voltage generating circuit 100 raises and drops internal voltage VIN by the prescribed quantity responding to activation of the control signals VUP and VDW respectively.