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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JP2004343470
Kind Code:
A
Abstract:

To provide a semiconductor integrated circuit device capable of miniaturizing a circuit structure while suppressing the deterioration of a slew rate of an output signal and of realizing excellent signal amplification characteristics even when the device is suitable for an operational amplifier or the like as an integrated circuit in the integrated circuit constituted by applying a low-temperature poly-silicon transistor.

A CMOS operational amplifier 100 has a structure in which a first amplifier circuit part APA and a second amplifier circuit part APB are connected in parallel between a first input terminal Ti1, a second input terminal Ti2, and an output terminal Tout. Also, a high potential voltage Vdd and a low potential voltage Vss are applied as source voltages to the first amplifier circuit part APA and the second amplifier circuit part APB respectively, and bias voltage setting parts 10A and 10B, differential amplification parts 20A and 20B, and output amplifier parts 30A and 30B are connected between the high potential voltage Vdd and the low potential voltage Vss.


Inventors:
YAMAMOTO TAKUMI
KANBARA MINORU
Application Number:
JP2003138209A
Publication Date:
December 02, 2004
Filing Date:
May 16, 2003
Export Citation:
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Assignee:
CASIO COMPUTER CO LTD
International Classes:
H01L29/786; H03F3/45; H03F3/68; H03K19/0175; (IPC1-7): H03F3/45; H01L29/786; H03F3/68; H03K19/0175
Attorney, Agent or Firm:
Hidemi Kashima