Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JP3155946
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device where a device such as a single electronic transistor and a device such as a conventional CMOS can be mixedly mounted by fully utilizing each feature.
SOLUTION: In a semiconductor integrated circuit device that uses a silicon substrate 11 and an SOI substrate consisting of a buried insulation film 12 that is formed on the silicon substrate 11 and a surface silicon layer 13 that is formed on the buried insulation film 12, at least one of semiconductor devices 32a and 32b is formed on the silicon substrate 11, and at least one of semiconductor devices 31a and 31c is formed on the surface silicon layer 13. A semiconductor device 31 that is formed on the silicon layer operates with a power voltage that is smaller than that of a semiconductor device 32 being formed on the semiconductor substrate.
Inventors:
Ken Uchida
Akira Toriumi
Akiko Ohata
Junji Koga
Akira Toriumi
Akiko Ohata
Junji Koga
Application Number:
JP35885797A
Publication Date:
April 16, 2001
Filing Date:
December 26, 1997
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L29/78; H01L27/08; H01L29/66; H01L29/786; H01L49/00; (IPC1-7): H01L27/08; H01L29/66
Domestic Patent References:
| JP8102498A | ||||
| JP521706A | ||||
| JP3148852A | ||||
| JP8288505A |
Attorney, Agent or Firm:
Takehiko Suzue (6 outside)