Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JP3164067
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To realize a high integration of a semiconductor integrated circuit device and to prevent deterioration of characteristics of each transistor in the adjacent-arranged unit cells, by removing minute opposing regions between a plurality of unit cells arranged adjacent.
SOLUTION: Regions defined by boundary lines LX and LY of X and Y directions includes at least a well region WN of a one conductivity type, well contact regions WCAN of the same conductivity type as unit cells C4 to C8 are arranged in the well region WN, the cells are arranged in an X direction (or Y direction) so that boundary lines LY of the adjacent unit cells are mutually overlapped, and the well contact regions WCAN are formed as contacted with the boundary lines LY of the unit cells adjacent in the above array direction. No minute opposing regions can be formed between the well contact regions WCAN of the adjacent unit cells an array dimension of the unit cells in the X direction can be reduced thus realizing a high integration. Further a transistor having an accurate region can be formed without causing falling of a photoresist film in a photoresist step.
Inventors:
Tsutomu Furuki
Application Number:
JP19853398A
Publication Date:
May 08, 2001
Filing Date:
July 14, 1998
Export Citation:
Assignee:
NEC
International Classes:
H01L27/092; H01L21/82; H01L21/8238; (IPC1-7): H01L21/82
Domestic Patent References:
| JP498876A | ||||
| JP7202144A |
Attorney, Agent or Firm:
Suzuki Akio