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Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPH02105451
Kind Code:
A
Abstract:

PURPOSE: To enhance reliability of a semiconductor integrated circuit device with a built-in circuit for trimming code setting use by a method wherein a plurality of series bodies composed of a transistor and a thin-film resistance are prepared in order to decide one trimming code and a logical sum of their outputs or an inversion of the logical sum is used.

CONSTITUTION: A circuit for trimming code setting use individually takes, at NOR gates 8, 9, 10, an inversion of a logical sum of source outputs of two each of transistors for each set out of three sets of ratio circuits composed of the following: thin film resistances 11, 12, 13, 14, 15, 16 of polysilicon or the like; P-channel MOS type transistors 3, 4, 5, 6, 7. When the resistances 13, 14 are cut, nodes 19, 20 are set at a potential of a logical threshold value or higher of the NOR gate 9 by the transistors 4, 5; the NOR gate outputs a low (LOW) and the trimming code can be set.


Inventors:
HINOOKA KIYONOBU
Application Number:
JP25870688A
Publication Date:
April 18, 1990
Filing Date:
October 13, 1988
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L27/04; H01L21/82; H01L21/822; (IPC1-7): H01L21/82; H01L27/04
Attorney, Agent or Firm:
Uchihara Shin