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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPH02105532
Kind Code:
A
Abstract:

PURPOSE: To eliminate the restriction to a layout by removing any influence of noise by surrounding and shielding the side and bottom of a current wiring with a conductive material whose one end is connected to a low impedance point.

CONSTITUTION: A shielding plate comprising a phosphor-doped polycrystalline silicon layer 1 is inserted between a semiconductor substrate 4 and a high impedance wiring 2. Further there is formed a shielding plate on both sides of the high impedance wiring 2 by providing aluminum conductors 8 on both sides of the high impedance wiring 2 and connecting the aluminum conductors 8 and the phosphor-doped polycrystalline silicon layer 1 through a contact region 3. Hereby, another wiring can freely be provided in the vicinity of the high impedance wiring 2 to eliminate the restriction to a layout.


Inventors:
HINOOKA KIYONOBU
Application Number:
JP25847588A
Publication Date:
April 18, 1990
Filing Date:
October 14, 1988
Export Citation:
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Assignee:
NEC CORP
International Classes:
G12B17/02; G06J1/00; H01L21/3205; H01L21/768; H01L21/822; H01L23/52; H01L23/522; H01L23/552; H01L27/04; H05K9/00; (IPC1-7): G06J1/00; G12B17/02; H01L21/3205; H01L21/90; H01L27/04; H05K9/00
Domestic Patent References:
JPS6151847A1986-03-14
JPS63268257A1988-11-04
JPH022623A1990-01-08
JPH0265240A1990-03-05
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
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