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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPH03222467
Kind Code:
A
Abstract:

PURPOSE: To absorb noise though a high impurity concentration layer and to prevent propagation of noise to circuits subjected to noise by so forming a high impurity concentration layer of the same conductivity as a first well on a substrate as to wrap the first well, and equalize the potential of the high impurity concentration layer with those of the substrate and the first well.

CONSTITUTION: A P+ layer 12 being the high impurity concentration layer of the same conductivity as a first P-type well 2 is formed at a P-type semiconductor substrate, wrapping the first P-type well 2 where a digital circuit is formed, and this is earthed similar to the substrate 1 and the first P-type well 2 so as to bring them into same potential. In this case, the resistance value of the equivalent resistance 13 of the P+ layer 12 is smaller than those of other equivalent resistances 5∼7, so the noise arising in the digital circuit as a noise source is propagated to the earth through the equivalent resistance 5 of the P-type well 2 and the equivalent resistance 13 of the P+ 12, and it can be prevented from being propagated to an analog circuit though the substrate 1. Hereby, the circuit subjected to noise can be prevented from malfunctioning due to noise, whereby a high reliability of semiconductor integrated circuit can be gotten.


Inventors:
ANDO HIDEKI
MACHIDA HIROHISA
Application Number:
JP1945690A
Publication Date:
October 01, 1991
Filing Date:
January 29, 1990
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L21/761; H01L21/822; H01L27/04; H01L27/08; H01L27/02; (IPC1-7): H01L21/76; H01L27/04; H01L27/08
Attorney, Agent or Firm:
Masuo Oiwa (2 outside)



 
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