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Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPH04103148
Kind Code:
A
Abstract:

PURPOSE: To make it possible to modify the size of a chip and to make it possible to enhance the freedom of the design of a circuit by a method wherein a signal from an input pad and a signal from an output buffer are respectively fed to output pads via respective diffused layers.

CONSTITUTION: A signal inputted through an input pad 4 is made to pass through a diffused layer 1 of a P-channel MOS transistor via an Al wiring 5. Moreover, the signal is made to pass through a diffused layer 2 of an N- channel MOS transistor, reaches an Al wiring 7 and is transmitted to the P- channel MOS transistor constituting an input buffer. As a result, the P-channel and N-channel MOS transistors are all held in an OFF-state and surge protective resistors are respectively formed of the respective layers 1 and 2. On the other hand, a signal from an output buffer is made to pass through a diffused layer 22 of an N-channel MOS transistor via an Al wiring 25. Moreover, the signal is made to pass through a diffused layer 21 of a P-channel MOS transistor, reaches the Al wiring 25 and is transmitted to an output pad 24. Surge protective resistors are respectively formed of the respective layers 21 and 22.


Inventors:
KAMANAKA HISANORI
Application Number:
JP22222890A
Publication Date:
April 06, 1992
Filing Date:
August 22, 1990
Export Citation:
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Assignee:
MATSUSHITA ELECTRONICS CORP
International Classes:
H01L27/118; H01L21/82; H01L23/62; (IPC1-7): H01L21/82; H01L23/62; H01L27/118
Attorney, Agent or Firm:
Miyai Akio