SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - MITSUBISHI ELECTRIC CORP

Title:

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Document Type and Number:

Japanese Patent JPH04914

Kind Code:

A

Abstract:

PURPOSE: To reduce the number of mounting parts and to miniaturize a mounting substrate by using a transistor not used in an output buffer in LSI as a dump resistance instead of a dump resistance for external fitting.

CONSTITUTION: An internal signal terminal 1 is connected to a gate 2a of a P channel transistor 2, and a source 2b to a power source terminal 3 and a drain 2c to a source 5b of an N channel transistor 5. A gate 5a of the N channel transistor 5 is connected to the power source terminal 3 and a drain 5c to a bonding pad 4. Thus, in a conventional equivalent circuit, a dump resistance 9 is replaced by the resistance of the transistor between the source 5b and the drain 5c of the N channel transistor 5 usually in an ON state because the gate 5 is connected to the power source terminal 3.

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Inventors:

YONEZU AKIRA

Application Number:

JP10270290A

Publication Date:

January 06, 1992

Filing Date:

April 18, 1990

Export Citation:

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Assignee:

MITSUBISHI ELECTRIC CORP

International Classes:

H03K19/173; H03K19/0185; H03K19/094; H03K19/0952; (IPC1-7): H03K19/173; H03K19/0185; H03K19/094; H03K19/0952

Domestic Patent References:

JPS6319915A	1988-01-27
JPH01228214A	1989-09-12

Attorney, Agent or Firm:

Kaneo Miyata (3 outside)

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