PURPOSE: To easily define an input/output terminal without loading any burden to a software at the semiconductor integrated circuit device.
CONSTITUTION: A first shift register circuit part 1 inputs a serial data input SI. A latch circuit part 2 latches respective bit data S0-S3 of the serial data input SI of the shift register circuit part 1. Respective input/output circuit parts 3 output respective latch data latched by the latch circuit part 2 from respectively correspondent input/output terminals P0-P3 as parallel data D0-D3. A second shift register circuit part 4 is connected to the respective input/output circuits 3. A selection part 5 holds input/output state data being any one of an input circuit and an output circuit concerning the respective input/output circuit parts 3. The respective input/output circuit parts 3 are turned to any one of the input circuit and the output circuit based on these input/output state data.
WO/2007/041141 | CIRCUIT AND METHOD FOR DETECTING NON-VOLATILE MEMORY DURING A BOOT SEQUENCE |
JPH11119975 | BIT WIDTH CONVERTER |
FUJITSU VLSI LTD
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