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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPH0722512
Kind Code:
A
Abstract:

PURPOSE: To increase the signal transmission rate and simplify layout by forming a first layer and a third layer superimposed each other and by connecting a second layer to any of the first layer and the second layer through a layer insulating film.

CONSTITUTION: A first layer and a third layer metallic wiring layers M1 and M3 are formed in a wiring region and, if an intermediate second wiring layer is made as wiring for connecting a signal bus to circuit block formed in the wiring region, then the mutual connection can be made easily for any of the first layer wiring layer M1 and the third layer wiring layer M3 only by removing a layer insulating film between them. By doing this, the contact between the wiring layer M2 and M1 or M2 or M3 is small and can be realized by a contact region. Also by the construction of the first layer wiring layer M1 superimposed to the third layer wiring layer M3 to be formed in the wiring region, the layer insulating film or wiring layer M2 can intervene thickly, by which the interference by signals can be reduced to a minimum.


Inventors:
SAEKI TETSUYA
MUSHA TATSUNORI
SUZUKI YUKIE
NASU TAKUMI
SUZUKI TOMOHIRO
Application Number:
JP1993000190892
Publication Date:
January 24, 1995
Filing Date:
July 02, 1993
Export Citation:
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Assignee:
HITACHI LTD
TEXAS INSTRUMENTS JAPAN
International Classes:
H01L21/82; H01L21/3205; H01L23/52; (IPC1-7): H01L21/82; H01L21/3205
Attorney, Agent or Firm:
徳若 光政



 
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