Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPH088359
Kind Code:
A
Abstract:

PURPOSE: To obtain a semiconductor integrated circuit device in which a countermeasure to noise can be taken for a high density, high speed BGA package by a structure wherein the connection of a capacitor or the formation of a dielectric layer serves as a noise killer.

CONSTITUTION: In a surface mounting BGA package, spherical solder bumps 2a-2c are arranged in array on the read side of a printed board 1 mounting a capacitor 4, as well as a semiconductor chip 3, on the surface thereof. The semiconductor chip 3 is connected through bonding wires 5a-5c with the solder bumps 2a-2c and sealed with a molding resin 6. The printed board 1 comprises a laminate of a power supply layer 7, a ground layer 8 and a signal layer 9 and the semiconductor chip 3 is connected through the bonding wires 5a-5c and through holes 10a-10c with the power supply layer 7, the ground layer 8 and the signal layer 9. The semiconductor chip 3 is also connected with the solder bumps 2a-2c and the capacitor 4 is connected through the through holes 10a, 10e with the power supply layer 7 and the ground layer 8.


Inventors:
OCHI YOSHISHIGE
SHIOZAWA KENJI
Application Number:
JP13919694A
Publication Date:
January 12, 1996
Filing Date:
June 21, 1994
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
HITACHI LTD
International Classes:
H01L23/12; (IPC1-7): H01L23/12
Attorney, Agent or Firm:
Yamato Tsutsui