To provide a semiconductor integrated circuit device that consists of a gate array type in a master slice system that solves logical expected value inequality at the time of an LSI test.

In an internal cell area 33 of a semiconductor integrated circuit device, basic cells 5 to 8, 13 to 16, 21 to 24 and 29 to 32 are arranged in a matrix shape, and drive capability variable circuits 1 to 4, 9 to 12, 17 to 20 and 25 to 28 are separately connected to the basic cells. Separately corresponding selective signal lines 101 to 104 are connected to the circuits 1 to 4, 9 to 12, 17 to 20 and 25 to 28, and also, separately corresponding control signal lines 105 to 108 are connected to the circuits 1, 9, 17 and 25, the circuits 2, 10, 18 and 26, the circuits 3, 11, 19 and 27 and the circuits 4, 12, 20 and 28.