Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS59155144
Kind Code:
A
Abstract:
PURPOSE:To facilitate the wiring between pads and cells in the four up-and- down and right-and-left directions by a method wherein the whole fundamental cell row is divided into four blocks, the row arrangement of two blocks having a diagonal relation to each other among the four block is set in the same direction and the row arragnement of other two blocks is set in one rotated in a 90 deg.. CONSTITUTION:The whole circuit is divided into four blocks on the basis of the relation with each pad in the X1, X2, Y1 and Y2 directions. A block having a strong intercorrelation with the pad in the X1 direction, a block having a strong intercorrelation with the pad in the X2 direction, a block having a strong intercorrelation with the pad in the Y1 direction and a block having a strong intercorrelation with the pad in the Y2 direction are respectively classified to A, D, C and B blocks. On the other hand, in each of the A, B, C and D blocks, a cell sharing an input and output terminal with the pad is arranged on the foremost out side and the input and output terminal between the pad and the cell is connected with a wiring.
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Inventors:
KAWAMURA MASAHIKO
Application Number:
JP2851783A
Publication Date:
September 04, 1984
Filing Date:
February 24, 1983
Export Citation:
Assignee:
TOSHIBA KK
International Classes:
H01L21/822; H01L21/82; H01L27/04; H01L27/118; (IPC1-7): H01L27/04
Attorney, Agent or Firm:
Noriyuki Noriyuki