Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS59165436
Kind Code:
A
Abstract:
PURPOSE:To achieve reduction of area of the chip or the high-density chip by increasing the arbitrariness regarding the size or arrangement of the block composed of active elements substantially by providing a power principal line above the power wiring arranged on the element region with meeting at right angles. CONSTITUTION:In case of a three-layer wiring of a large-scale integrated circuit, an element region is provided with function blocks 7 which are composed of CMOS cells as active elements and arranged in rows to compose blocks 6. A power wiring 4 is arranged by use of a first wiring layer and input and output terminals of the function blocks 7 and the blocks 6 are drawn out to a wiring region 2 by use of a second wiring layer. A power principal line 5, which is arranged in the direction to meet at right angles with the power wiring 4, is predetermined by use of a third wiring layer so as to lead the result; WMAX< WBK-dwX2, wherein WMAX is the maximum width of wiring of the power principal line, dw is a distance among the power source wirings and the minimum width of blocks is WBK.
Inventors:
OGAWA YUUKO
Application Number:
JP3911283A
Publication Date:
September 18, 1984
Filing Date:
March 11, 1983
Export Citation:
Assignee:
TOSHIBA KK
International Classes:
H01L21/3205; H01L21/82; H01L23/52; H01L27/118; (IPC1-7): H01L21/90
Attorney, Agent or Firm:
Noriyuki Noriyuki