PURPOSE: To provide a check mechanism in the inside of device by providing the 1st area and the 2nd area of the 2nd conductor type in the vicinity of an input terminal of an MOS inverter of the 1st stage and connecting the input terminal and the gate electrode of an enhancement transistor (TR) connected to the 1st area to the signal source in phase.

CONSTITUTION: N-channel diffusion layers 3, 7, 12 are formed to a P-channel silicon substrate 30, a gate oxide film 31 and a gate electrode 4 are formed on the suffusion layer 3 to form a capacitor. The gate electrode 4 is connected to the diffusion layer 7 and this area is connected to the substrate potential through an enhancement TR as a drain. The diffusion areas 7, 12 are not electrically connected at all normally and the potential of the diffusion layer region 7 is lowered than that of the substrate 30 by activating the level decrease circuit 100, a parasitic npn TR (regions 7-30-12) on the structure is activated and the charging in a gate capacitance connected to a diffusion region 12 is discharged momentarily.