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Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS6153776
Kind Code:
A
Abstract:

PURPOSE: To provide an MOS transistor having a fine construction, by forming a contact hole on a source/drain region without the need of any aligning allowance for the contact hole.

CONSTITUTION: A side wall 26 consisting of an Si nitride film is formed on the side wall of a polycrystalline Si gate electrode 24. Source and drain regions 27 are formed on the surface portions of a substrate 21 on the both sides of the electrode 24. An intermediate insulation film 28 consisting of Si dioxide is formed on the whole surface of the Si substrate 21 provided with the regions 27 and the like. The film 28 is provided with a contact hole 29 on the regions 27 such that it is contacted with the end of the side wall 26 without providing any aligning allowance. Source and drain electrodes 30 are formed on the film 28 such that they are connected with the regions 27 through the hole 29.


Inventors:
INOUE HIROSHI
Application Number:
JP17520884A
Publication Date:
March 17, 1986
Filing Date:
August 24, 1984
Export Citation:
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Assignee:
OKI ELECTRIC IND CO LTD
International Classes:
H01L29/417; H01L29/78; (IPC1-7): H01L21/28; H01L29/60
Attorney, Agent or Firm:
Toshiaki Suzuki (1 person outside)