Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS615545
Kind Code:
A
Abstract:
PURPOSE:To enable to perform the wirings among a number of logical elements in an orderly manner without substantially impairing spatial efficiency by a method wherein the wirings are provided by dividing them into two functional groups of common wirings and local wirings and, at the same time, the local wirings are wired with multiplayer wirings. CONSTITUTION:The wirings with which wire connections are performed between logical elements IILs are proided by dividing into two functional groups. One of them is the common wirings L11-L14 which are used to connected between IILs, and the other one is the local wirings L21 and L23 which are used to individually connect a plurality of electrodes B, c1, c2 and c3 located inside each IIL and the common wirings L11-L14. At the same time, a plurality of electrodes B, c1, c2 and c3 in each IIL are arranged two-dimensionally respectively. As a result, the four electrodes B, c1, c2 and c3 in each IIL do not have a positional interference each other, and they can be connected to any desired one of the common wirings L11-L14 through the intermediary of the local wiring L21 or L23.
Inventors:
MATSUDA TOSHIHIRO
Application Number:
JP12516284A
Publication Date:
January 11, 1986
Filing Date:
June 20, 1984
Export Citation:
Assignee:
HITACHI LTD
International Classes:
H01L27/082; H01L21/82; H01L21/8226; H01L23/528; H01L27/118; H03K19/091; (IPC1-7): H01L21/82; H01L27/08; H03K19/091
Attorney, Agent or Firm:
Akio Takahashi