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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS62183158
Kind Code:
A
Abstract:

PURPOSE: To reduce the layout area of the input protective circuit part of the titled device by a method wherein an input protective resistor is prevented from breakdown by providing voltage clamping diodes on both ends of the input protective resistor, and at the same time, at least one of the voltage clamping diodes is formed under the input protective resistor.

CONSTITUTION: An input protecting resistor R is formed using the resistance thin film 4 provided on the surface insulating film 3 of a semiconductor substrate 1, and at the same time, voltage clamping diodes D1 and D2 are connected to both ends of said resistor R respectively using a diffused layer 21. Besides, at least one of the diodes, namely, the diffusion layer 21 which constitutes the diode 2, for example, is formed under the resistance thin film 4, As a result, the generation of troubles such as a latch-up and the like can be suppressed, and the resistor R can be prevented from the breakdown due to the surge of excessive energy without enlarging the layout area of the input protective circuit part 20. Also, the breakdown-resisting strength can be enhanced as a whole.


Inventors:
ARAI YUJI
Application Number:
JP2374586A
Publication Date:
August 11, 1987
Filing Date:
February 07, 1986
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L29/78; H01L27/02; H01L27/06; (IPC1-7): H01L27/06; H01L29/78
Attorney, Agent or Firm:
Katsuo Ogawa



 
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