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Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS63208324
Kind Code:
A
Abstract:

PURPOSE: To prevent a current from flowing in from another power source system by composing the input protection circuit of an N channel MOS transistor (TR) and a resistance and an output circuit of an NPN bipolar TR and an N channel MOS TR respectively.

CONSTITUTION: The input protection circuit consists of an N channel MOS TR 14 which has its drain connected to a data input terminal 8, and its gate input, source, and back gate connected to a GND terminal 11 and the resistance 7 connected in series between the drain and input CMOS inverter. The output circuit consists of the NPN bipolar TR 17 which has its emitter connected to a data output terminal 9, its collector connected to a power source terminal 10, and its base connected to the output of the output CMOS inverter and the N channel MOS TR4 which has its drain connected to the output terminal 9, its source and back gate connected to the terminal 11, and its gate connected to the output of an internal circuit. Thus, a current is prevented from flowing in from another power source system and input electrostatic dielectric strength is prevented from decreasing.


Inventors:
OKIDAKA TAKENORI
Application Number:
JP4191887A
Publication Date:
August 29, 1988
Filing Date:
February 24, 1987
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L21/8238; H01L21/8249; H01L27/06; H01L27/092; H03K17/0812; H03K17/16; H03K19/003; H03K19/0175; H03K19/08; (IPC1-7): H01L27/06; H01L27/08; H03K19/00; H03K19/003
Domestic Patent References:
JPS6221323A1987-01-29
JPS6132562A1986-02-15
Attorney, Agent or Firm:
Kenichi Hayase