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Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS63310169
Kind Code:
A
Abstract:

PURPOSE: To reduce an element area and to realize a high-speed operation, by mounting a collector drawing electrode, which is formed of a polycrystalline silicon film doped with impurities, on side walls of a collector region in a bipolar transistor.

CONSTITUTION: After a polycrystalline silicon film 15 is formed on the whole surface, ion implantation of n-type impurities such as arsenic for example is performed in this silicon film 15. Next, together with annealing performed, the arsenic of ion implantation is diffused into the whole of the silicon film 15 and also diffused into an epitaxial layer 3 and a buried layer 2 through openings 11a, 12a, so that e.g., an n-type collector drawing region 16 is formed. Subsequently an insulation film 14 is removed and the polycrystalline silicon film 15 is formed into a prescribed shape. Heat oxidation of the surface of this silicon film 15 is performed to form an insulation film 18 such as an SiO2 film. After this heat oxidation, a collector drawing electrode 19 is composed of the polycrystal silicon film 15. This collector drawing electrode 19 is mounted with self-matching performance on side walls of a projecting part. Hence, an element area can be reduced and a high-speed operation can be realized.


Inventors:
OWADA NOBUO
ENAMI HIROMITSU
Application Number:
JP14504687A
Publication Date:
December 19, 1988
Filing Date:
June 12, 1987
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L29/73; H01L21/331; H01L29/72; H01L29/732; (IPC1-7): H01L29/72
Attorney, Agent or Firm:
Yamato Tsutsui