Title:
半導体集積回路装置
Document Type and Number:
Japanese Patent JP3993717
Kind Code:
B2
Abstract:
A semiconductor integrated circuit device includes a DLL circuit. The DLL circuit includes a frequency divider which frequency-divides an input clock at a frequency dividing ratio which is varied depending on a frequency of the input clock and thus results in a dummy clock and a reference clock. A delay system includes a variable delay circuit which delays the dummy clock. A control circuit controls a delay amount of the variable delay circuit so that a phase of a delayed dummy clock from the delay system and the reference clock becomes zero.
Inventors:
Fujieda Kazuichiro
Yasuharu Sato
Nobutaka Taniguchi
Hiroyuki Tomita
Yasuo Matsuzaki
Yasuharu Sato
Nobutaka Taniguchi
Hiroyuki Tomita
Yasuo Matsuzaki
Application Number:
JP16133199A
Publication Date:
October 17, 2007
Filing Date:
June 08, 1999
Export Citation:
Assignee:
富士通株式会社
International Classes:
G11C11/407; G11C11/4076; G06F1/08; G06F1/10; G11C7/10; G11C7/22; G11C11/406; H03K5/13; H03K5/135; H03K23/58; H03L7/00; H03L7/081
Domestic Patent References:
| JP10149227A | ||||
| JP10171774A | ||||
| JP10320976A |
Attorney, Agent or Firm:
Tadahiko Ito