Title:
半導体集積回路装置
Document Type and Number:
Japanese Patent JP4166103
Kind Code:
B2
Abstract:
A semiconductor integrated circuit device has a MOS transistor M 2 including a parasitic diode Dx 2 for preventing a reverse current due to a parasitic diode Dx 1 of a MOS transistor M 1 . The semiconductor integrated circuit device further has a voltage setting circuit 1 for turning the MOS transistor M 2 off in a reversely biased state, and an anti-reverse-current element 2 for preventing a reverse current from flowing through the voltage setting circuit 1 in a reversely biased state. In normal operation, a direct-current voltage within the withstand voltage range of the MOS transistor M 2 is fed to the gate thereof according to the voltage applied to the conductive terminal 6 y of the MOS transistor M 2.
Inventors:
Nobuhiro Nishikawa
Koichi Inoue
Koichi Inoue
Application Number:
JP2003050643A
Publication Date:
October 15, 2008
Filing Date:
February 27, 2003
Export Citation:
Assignee:
ROHM Co., Ltd.
International Classes:
H01L21/822; H01L27/04; H01L21/00; H01L21/8234; H01L23/62; H01L27/00; H01L27/088; H01L29/76; H02H3/24; H03K17/00; H03K17/10; H03K17/24; H03K19/003; H01L27/02
Domestic Patent References:
| JP60163113A | ||||
| JP11087628A |
Attorney, Agent or Firm:
Shizuo Sano