Title:
半導体集積回路装置
Document Type and Number:
Japanese Patent JP6974743
Kind Code:
B2
Abstract:
Provided is a semiconductor integrated circuit device including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the device easy. A standard cell having no logical function is disposed adjacent to a standard cell having a logical function. The standard cell includes nanowire FETs having nanowires and pads. The standard cell further includes dummy pads, which have no contribution to a logical function of a circuit.
Inventors:
Hiroyuki Shinbo
Application Number:
JP2018531797A
Publication Date:
December 01, 2021
Filing Date:
July 07, 2017
Export Citation:
Assignee:
Socionext Inc.
International Classes:
H01L21/82; H01L21/822; H01L21/8234; H01L21/8238; H01L27/04; H01L27/06; H01L27/088; H01L27/092; H01L29/06
Domestic Patent References:
| JP2015019067A | ||||
| JP2015015502A |
Foreign References:
| WO2015033490A1 | ||||
| WO2009150999A1 | ||||
| US20160079358 |
Attorney, Agent or Firm:
Maeda patent office
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