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Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED CIRCUIT ESTIMATION DEVICE
Document Type and Number:
Japanese Patent JP2004234187
Kind Code:
A
Abstract:

To rapidly decide whether a semiconductor integrated circuit chip can be mounted in a package or not by enabling decision of whether the chip can be mounted in the package without calculation of a layout of the a semiconductor integrated circuit.

When specification information about specifications of the semiconductor integrated circuit is inputted from an input device 101, a CPU 102 calculates a circuit scale of the semiconductor chip and the number of the chips collectable from one wafer, and decides whether the semiconductor integrated circuit chip can be mounted in the package or not, by use of design information (package information, a macro library, mounting macro information, layout restriction) from a magnetic disk 105, before the layout of the semiconductor integrated circuit. Thereafter, the CPU 102 reads an automatic layout rule, calculates the layout, and converts the layout into a prescribed format to output the layout.


Inventors:
TSUTSUMI YASUO
SUZUKI KENSUKE
KATO MASAHIRO
Application Number:
JP2003020176A
Publication Date:
August 19, 2004
Filing Date:
January 29, 2003
Export Citation:
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Assignee:
JEDAT INC
International Classes:
G06F17/50; H01L21/82; (IPC1-7): G06F17/50; H01L21/82