SEMICONDUCTOR INTEGRATED CIRCUIT AND FREQUENCY MODULATING DEVICE

Title:

SEMICONDUCTOR INTEGRATED CIRCUIT AND FREQUENCY MODULATING DEVICE

Document Type and Number:

Japanese Patent JP2005312004

Kind Code:

A

Abstract:

To suppress to approximately 0 a leakage current of a target node, of which potential is wished to be held for a predetermined period while it is kept in floating, and to suppress potential variation of the target node.

The semiconductor integrated circuit comprises a transistor QN0 for switching connected between a first node N1 and a second node N2, a switch element S1 and a switch element S2 for switching potential of a substrate of the transistor for switching, and a buffer circuit G1 which outputs a same potential as a potential of the second node is inputted. The switch element S2 is controlled to connect the substrate of the transistor for switching to an output node of the buffer circuit for at least a part of a period when the transistor for switching is turned off.

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Inventors:

TANZAWA TORU

Application Number:

JP2004204851A

Publication Date:

November 04, 2005

Filing Date:

July 12, 2004

Export Citation:

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Assignee:

TOSHIBA CORP

International Classes:

H01L21/8238; H01L27/02; H01L27/04; H01L27/092; H01L27/108; H01L29/76; H03B5/12; H03C3/00; H03K3/03; H03K3/354; H03K17/06; H03K17/687; H01L21/822; H03L7/089; H03L7/093; H03L7/18; (IPC1-7): H03C3/00; H01L21/822; H01L21/8238; H01L27/04; H01L27/092; H03B5/12; H03K3/03; H03K3/354; H03K17/06; H03K17/687; H03L7/093

Attorney, Agent or Firm:

Takehiko Suzue
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto

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