To shorten check time and to improve check efficiency concerning a consolidation type semiconductor integrated circuit provided with a memory and a logic.
A consolidation type semiconductor IC 11 equipped with a DRAM 12 and a logic 13 is provided with a checked result recording circuit 15 constituted by using techniques used for the DRAM 12. After the first memory check is executed, the checked result is written in the recording circuit 15. When executing the next logic check, on the first stage, the checked result written in the recording circuit 15 is read out and the logic check is performed only concerning a non-defective. Thus, concerning the defective of the memory check, time for performing the logic check can be reduced and check efficiency can be improved.
| WO/1998/054649 | DISTRIBUTED LOGIC ANALYZER FOR USE IN A HARDWARE LOGIC EMULATION SYSTEM |
| WO/1997/033180 | PROBE FOR FAULT ACTUATION DEVICES |
| JP3261800 | INTEGRATED CIRCUIT FOR DRIVING DISPLAY PANEL |
SHIGEUCHI SATOSHI
SAKAMOTO SHOJI
SHIMAKAWA KAZUHIKO
OTA KIYOTO
